With the high-integration of semiconductor devices, known metals such as tungsten, copper, or alloys thereof have been turned out to be unsuitable for an interconnect material of a semiconductor device because they have a high specific resistance and cause electro migration (EM) or stress migration (SM), thereby deteriorating reliability of the semiconductor device. EM is a defect due to the increase in current density within a metal interconnect. In other words, EM is created because the current density increases by high-speed operation of the semiconductor device according to a fine interconnect pattern. SM is a creep rupture (failure) mode caused by imposing tensile mechanical stress on the metal interconnect. The mechanical stress is created by the difference in thermal expansion coefficient between the metal interconnect and an insulating layer to protect the metal interconnect. The mechanical stress increases as the width of the metal interconnect becomes narrower.
To obviate the above-mentioned problems, copper has been suggested as an alternative for known interconnect materials. Copper has a low specific resistance and ensures reliability of a semiconductor device. In addition, copper alloy has high corrosion-resistance and ensures reliability of the interconnect although it has a relatively high specific resistance in comparison with copper.
A copper dual damascene process, which inlays metal in an interconnect line, has been developed as an alternative because efforts to improve a copper etching method proved to be unsuccessful. The copper dual damascene process has been verified as an excellent process in terms of process affinity and cost reduction although it had been confronted with barriers in terms of apparatus due to completely different structures and across-the-board changes.
FIGS. 1a through 1d are cross-sectional views illustrating a known process of fabricating a copper interconnect of a semiconductor device. Referring to FIG. 1a, an insulating layer 10 is deposited on a substrate with at least one predetermined structure. A trench and via hole is formed through the insulating layer 10 by using a dual damascene process. A barrier layer 11 is then deposited along the bottom and the sidewalls of the trench and via hole. The trench and via hole is filled with copper by using an electrochemical plating (ECP) process and then planarized by using a chemical mechanical polishing (CMP) process to complete a lower copper interconnect 12.
Referring to FIG. 1b, a SiN layer is deposited over the structure of FIG. 1a to form a capping layer 13. The SiN layer has a thickness of about 700 Å. Referring to FIG. 1c, an interlayer dielectric (ILD) layer 14 is deposited on the capping layer 13. Referring to FIG. 1d, some portion of the ILD layer 14 and capping layer 13 is removed by an etching process using a predetermined pattern to form a via hole. The via hole is then filled with a conductive material to complete a via 15.
However, the above-described known method of forming a copper interconnect has several problems. First, if there is an oxidized area on the surface of the copper interconnect, the adhesion between the copper interconnect and the capping layer weakens and, as a result, the SiN layer as the capping layer 13 loosens. Constantly, the copper of the interconnect is diffused into the portion in which the SiN layer gets loose. Such copper diffusion may cause a short circuit between interconnects. Second, when the via is formed to connect the upper and lower interconnects, the upper interconnect may not be connected with the lower interconnect if the SiN layer as the capping layer within the via hole is completely removed. Third, the SiN layer may raise the total dielectric constant of the upper and lower interconnects because the SiN layer itself has a high dielectric constant.